1. Field of the Invention
The present invention is directed to a mask read only memory (ROM) which permits the entry of storage data designated by a user into the ROM and in particular to a mask ROM having a memory cell which is comprised of a field effect transistor.
2. Description of the Prior Art
Prior art mask ROM's which permit the entry of designated storage data, generally employ a system wherein the storage data designated by the user is entered by the manufacturing step, thereby enabling the manufacturer of the ROM to complete as much of the manufacturing as possible and only then have to enter the storage data in accordance with the particular user requirements. However, in prior art manufacturing processes of this type, the integration density of the memory is relatively low.
FIGS. 1 and 2 illustrate a prior art mask ROM in which the storage data is stored as existence or absence of an electrode contact window.
Referring to FIG. 1, word address signals A.sub.0 . . . A.sub.n are supplied to an address buffer AB.sub.1. The address buffer AB.sub.1 changes the levels of the word address signals. A word decoder selects one of the word line drivers WD.sub.1 . . . WD.sub.l in accordance with the output of the word address buffer AB.sub.1. The selected word line driver makes the level of the selected word line W.sub.1 -W.sub.l at a high level and the non-selected word lines remain at a low level.
An address buffer AB.sub.2 receives bit address signals B.sub.0 . . . B.sub.m and changes the levels of these signals, and a bit line selector receives the output of the address buffer AB.sub.2 and provides an output to the bit lines (read data) designated by the bit address signals B.sub.0 . . . B.sub.m. A signal .phi. is used for precharging the bit lines during the standby period.
A memory cell of the mask ROM comprises an enhancement type MOS FET Q1 where the gate electrode is connected to selected word line W.sub.i and an enhancement-type MOS FET Q2 in which the gate electrode is connected to the non-selected word lines. The sources S of FET's Q1 and Q2 are grounded while the drains D are selectively connected to the selected bit lines B.sub.n via the electrode contact window N. The storage data designated by the user is entered into the memory cell in accordance with the existence or non-existence of the electrode contact window N at the drain portion connected to the bit line. On the other hand, the stored data is read by setting the selected word line Wi and the bit line Bi high (H) level while the non-selected word lines and the bit lines remain at low (L) level. The forming or non-forming of contact windows is accomplished by using a mask having a pattern corresponding thereto. The FET Q1 thus becomes conductive allowing a current to flow from the voltage source V.sub.DD to the ground, making the potential of the bit line B.sub.i low. In the case where the electrode contact window N is not formed at the drain portion of FET Q1, FET Q1 cannot conduct the current from V.sub.DD and the potential of the bit line B.sub.i remains at high level.
Since the drain portions of FET's Q1 and Q2 of the memory cells have independent patterns, the pattern area is (28.mu..times.9.mu.), which results in a reduction in the integration density of the ROM pattern.